1. Field of the Invention
The invention relates to a memory device and more particularly to a phase change memory (PCM) device and a method for fabricating the same.
2. Description of the Related Art
Phase change memory devices are non-volatile, highly readable, highly programmable, and require a lower driving voltage/current. Current phase change memory device topics of interest include increasing cell density and reducing current density.
Phase change material in a phase change memory device has at least two solid phases, a crystalline state and an amorphous state. Transformation between these two phases can be achieved by changing the temperature of the phase change material. The phase change material exhibits different electrical characteristics depending on state. For example, in an amorphous state, the material exhibits a higher resistivity than in a crystalline state. Such phase change material may switch between numerous electrically detectable conditions of varying resistivity on a nanosecond time scale with the input of pico joules of energy. Chalcogenide material is a popular and widely used phase change material in modern phase change memory technology.
Since phase transformation of the phase change material is reversible, a bit status of a memory device can be distinguished by differences in resistivity of the phase change material in a PCM device in a crystalline state and an amorphous state.
FIG. 1 is a cross section view of a conventional phase change memory (PCM) cell. As shown in FIG. 1, an isolation structure 13 is located at a predetermined region of a semiconductor substrate 11 to thereby define an active region. A source region 17s and a drain region 17d are disposed apart in the active region. A gate 15, functioning as a word line, is disposed across the active region between the source region 17s and the drain region 17d. The gate 15, the source region 17s and the drain region 17d form an transistor. The semiconductor substrate 11 having the transistor thereon is covered with an insulating layer 19. An interconnection line 21 is disposed over the first insulating layer 19. The interconnection line 21 is electrically connected to the drain region 17d through a contact hole penetrating the first insulating layer 19. Another insulating layer 23 covers the interconnection line 21. A heating plug 25 is disposed in the insulating layers 19 and 23, electrically connecting the source region 17s. A patterned phase change material layer 27 and a top electrode 29 are sequentially stacked over the insulating layer 23, wherein a bottom surface of the phase change material layer pattern 27 is in contact with the heating plug 25. Another insulating layer 31 is disposed on the insulating layer 23. A bit line 33 is located on the insulating layer 31 and is in contact with the top electrode 29.
In a write mode, the transistor is turned on and a large current flows through the heating plug 25, thus heating up an interface between the phase change material layer pattern 27 and the heating plug 25, thereby transforming a portion 27a of the phase change material layer 27 into either the amorphous state or the crystalline state depending on the length of time and amount of current that flows through the heating plug 25.
One problem found with conventional phase change transistor as shown in FIG. 1 is the relatively large amount of current required to successfully change the state of the phase change material during a write operation. One solution to increasing current density is to reduce a diameter D of the heating plug 25. There is still a limitation in the amount of reduction possible to the diameter D of the heating plug 25 because a photolithographic process determines the minimum diameter D. It is difficult to consistently produce a smaller diameter heating plug 25 due to limitations in the present photolithographic process.